In integrated circuit (IC) design, a design technique known as “data path” is used, in which a bus passes through one macro cell after another, with each macro cell performing particular operations on the bus signals. A macro cell generally is a rectangular, tiled arrangement of leaf cells which performs a function, such as ‘register’, ‘and’ or ‘add’ logical functions on the bus signals. The data path design technique reduces routing complexity of the buses because each bus line enters one side of a cell of the macro cell and exits the opposite side of the cell of the macro cell. For example, assuming the IC comprises two 64-bit buses, a macro cell may comprise 64 cells, each of which comprises an AND gate. Two lines from each of the 64-bit buses pass through each respective cell and the corresponding signals on the two lines are ANDed together. The lines of the buses then exit the opposite side of the cell with signals on them that depend on the operation(s) performed by the cell. Other examples of macro cells include a macro cell having 64 flip flops, 64 exclusive NOR gate (XNOR), etc.
When an IC is designed in this manner with macro cells, the design is normally tiled because the macro cells are designed with respect to the width of the bus, or buses, such that the bus lines enter the top of a cell and exit the bottom of a cell and continue on to, for example, the next macro cell. Therefore, the IC will typically comprise a large number of these macro cells arranged symmetrically. Generally, before the IC is ever designed, a library of data path macro cells is created so that the IC designer will have a full set of macro cells that provide for various types of functionality to work with when designing the IC. The IC designer then builds the data path block, which generally is a stack of the macro cells with appropriate connections made to all of the macro cells and the cells of the macro cells.
Data path macro cells (macro cells) are typically created using a macro cell generator program. This macro-cell generator program is written by the IC designer by hand using a programming language, such as, for example, C, C++ or PERL. The macro cell generator program is used to generate data representing a graphical representation of the layout of the macro cell. Using the macro cell generator program, an IC designer individually places each element of a macro cell in the layout, along with data indicating each signal name and a documentation layer. Loops are typically included in the macro cell generator program to allow the IC designer to provide for various widths (data bus widths) of the macro cell. This process requires a great deal of time and effort to define the macro cell by determining the position/function of each element of the macro cell and then translating that information so that it can be incorporated into the macro cell generation program. Additionally, once the macro cell generation program is written, making changes to the macro cell layout is very difficult, as the macro cell generation program cannot be easily changed and thus requires the IC designer to re-write substantial portions of the program to generate a macro cell having the changed/desired characteristics. Thus, it is typical that a new macro cell generation program must be written in order to provide for a macro cell having different characteristics.
Accordingly, a need exists for a system to automate generation of a data path macro cell.